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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document from Analog Marketing: MC34923/D Rev 0, 05/2003
Preliminary Information Full-Bridge PWM Motor Driver
Designed with Motorola's advanced SMARTMOS, the 34923 is designed for pulse-width modulated (PWM) current control of DC motors. It is capable of continuous output currents up to 2.0 A and operating voltages of up to 45 V. Internal fixed off-time PWM current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed current-decay modes. DIR and PWM/ENABLE input pins are provided for use in controlling the speed and direction of a DC motor with externally applied PWM-control signals. The PWM/ENABLE input can be programmed via the serial port to PWM the bridge in fast or slow current decay. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis and crossover-current protection. A special power-up sequencing is not required. Features * 2.0 A, 45 V Continuous Output Rating * Low RDS(ON) Outputs (270 m, typical) * Programmable Mixed, Fast, and Slow Current-Decay Modes * Serial Interface Controls Chip Functions * Synchronous Rectification for Low Power Dissipation * Internal Undervoltage Lockout Thermal Shutdown Circuitry * Crossover-Current Protection
34923
FULL-BRIDGE PWM MOTOR DRIVER
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DW SUFFIX 24-LEAD SOICW CASE 751E-04
ORDERING INFORMATION
Device MC34923DW/R2 Temperature Range (TA) -40 to 125C Package 24 SOICW
34923 Simplified Application Diagram
5.0 V 34923
5.0 V
PWMMODE DIR DCMA PWM/ENABLE MCU Serial Port CLOCK DATA STROBE OSC GND DCMB DC Motor
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc. 2003
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45 V
5.0 V CP1 CP2 VDD Bandgap VDD Thermal Shutdown Undervoltage and Fault Detect OSC (160 kHz) VB VBB Bandgap Regulator VREG
Charge Pump
Control Logic PWMMODE Direction Enable Sync. Rect.Control Internal PWM Mode External PWM Mode DCMA Gate Drive DCMB SENSE
Zero Current Detect
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DIR PWM/ENABLE
Motor
CS RS
OSC
Programmable PWM Timer
Fixed-Off Blank Decay
Current Sense
CLOCK DATA STROBE SPAN
Serial Port
Sleep Mode
Reference Buffer and Divider
VREF Load Current Reference
Figure 1. 34923 Simplified Block Diagram
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.
VB CP2 CP1 DIR OSC GND GND VDD PWM/ENABLE DATA CLOCK STROBE
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
VREG SPAN NC DCMB VBB GND GND SENSE DCMA NC PWMMODE VREF
PIN FUNCTION DESCRIPTION
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Pin 1 2 3 4 5 6, 7, 18, 19 8 9 10 11 12 13 14 15, 22 16 17 20 21 23 24
Pin Name VB CP2 CP1 DIR OSC GND VDD PWM/ENABLE DATA CLOCK STROBE VREF PWMMODE NC DCMA SENSE VBB DCMB SPAN VREG
Formal Name Boost Voltage Switching Capacitor 2 Switching Capacitor 1 Direction Oscillator Ground Logic Voltage H-Bridge Enable Serial Data Serial Data Clock Serial Data Latch Strobe Current Limit Reference Voltage PWM Mode Control No Connect H-Bridge Output A Current Sense H-Bridge Voltage Supply H-Bridge Output B Current Limit Reference Range Bandgap Voltage Boost voltage storage node.
Definition
Charge pump capacitor connection 2. Charge pump capacitor connection 1. Logic-level input for direction control. Logic-level oscillator (square wave) input. Ground. Low voltage (typically 5.0 V) logic supply. Logic-level input for enabling the H-bridge driver. Logic-level input for serial interface. Logic-level input for serial port (data is entered on rising edge). Logic-level input for serial port (active on rising edge). Load current reference input voltage. Logic-level input for PWM mode control when in internal PWM mode. No internal connection to this pin. One of two bridge outputs to the motor. Sense resistor. High-current (20 V to 45 V) load supply. One of two bridge outputs to the motor. Logic-level input for VREF range control. Bandgap decoupling capacitor.
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating Load Supply Voltage Logic Supply Voltage Input Voltage Sense Voltage Reference Voltage Output Current (Note 1) Storage Temperature Symbol VBB VDD VIN VS VREF IOUT TS TA TJ PD Value 48 7.0 -0.3 to VDD + 0.3 0.5 2.7 2.0 -55 to 150 -20 to 85 -40 to 150 1.6 (Note 3) Unit V V V V V A C C C W V VESD1 VESD2 TSOLDER RJA 2000 200 260 56 C C/W
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Ambient Temperature Operating Junction Temperature Power Dissipation (TA = 25C) (Note 2) ESD Voltage Human Body Model (Note 4) Machine Model (Note 5) Lead Soldering Temperature (Note 6) Thermal Resistance Junction-to-Ambient (Note 2)
Notes 1. Output current rating may be limited by duty cycle, ambient temperature, and heatsinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C. 2. Maximum power dissipation at indicated ambient temperature in free air with no heatsink used. 3. Per SEMI G42-88 specification. 4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). 5. 6. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). Lead soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions TA = 25C, VBB = 45 V, VDD = 5.0 V, VSENSE = 0.5 V, and fPWM < 50 kHz unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
OUTPUT DRIVERS
Load Supply Voltage Range Operating During Sleep Mode Output Leakage Current VOUT = VBB VOUT = 0 V IDSS - - RDS(ON) - - - - VF - - IBB - - - 4.0 2.0 - 7.0 5.0 20 mA mA 1.2 1.2 1.6 1.6 300 - 300 - 450 700 450 700 V <1.0 <-1.0 20 -20 m VBB 20 0 - - 45 45 V
A
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Output On Resistance Source Driver, IOUT = -2.0 A @ 25C Source Driver, IOUT = -2.0 A @ 150C Sink Driver, IOUT = 2.0 A @ 25C Sink Driver, IOUT = 2.0 A @ 150C Body Diode Forward Voltage Source Diode, IF = -2.0 A Sink Diode, IF = 2.0 A Load Supply Current fPWM < 50 kHz Charge Pump On, Outputs Disabled Sleep Mode
A
CONTROL LOGIC
Logic Supply Voltage Range (Operating) Logic Input Voltage VIN(1) VIN(0) Input Current All Logic Inputs Except PWM/ENABLE VIN = 2.0 V VIN = 0.8 V PWM/ENABLE Only VIN = 2.0 V VIN = 0.8 V Input Hysteresis All Digital Inputs Except OSC OSC (Operating) Reference Input Voltage Range (Operating) Reference Input Current VREF = 2.5 V Input Offset Voltage Comparator VREF = 0 V Buffer VIO - - 0 0 5.0 15 IIN(1) IIN(0) - - 40 16 100 40 mV IIN(1) IIN(0) - - <1.0 <-2.0 20 -20 2.0 - - - - 0.8 VDD 4.5 5.0 5.5 V V
A
VIN(LOGIC) VIN(OSC)
VREF IREF
50 200 0
- - -
100 400 2.6 V
A
- - 0.5 mV
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STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions TA = 25C, VBB = 45 V, VDD = 5.0 V, VSENSE = 0.5 V, and fPWM < 50 kHz unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
CONTROL LOGIC (continued)
Reference Divider Ratio Bit D14 = High Bit D14 = Low Thermal Shutdown Temperature Thermal Shutdown Hysteresis Undervoltage Lockout Enable Threshold TJ - 9.9 4.95 - - 10 5.0 165 15 10.2 5.05 - - C C V 3.90 4.2 0.10 4.45 - V mA - - 6.0 - 10 2.0 -
TJ
UVLO
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Increasing VDD Undervoltage Lockout Hysteresis Logic Supply Current fPMW < 50 kHz Sleep Mode, Inputs <0.5 V
UVLO
IDD
0.05
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DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions TA = 25C, VBB = 45 V, VDD = 5.0 V, VSENSE = 0.5 V, and fPWM < 50 kHz unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
CONTROL LOGIC
OSC Input Frequency (Operating) OSC Input Duty Cycle (Operating) Propagation Delay Times PWM Change to Source ON PWM Change to Source OFF PWM Change to Sink ON PWM Change to Sink OFF Direction Change to Sink ON Direction Change to Sink OFF Direction Change to Source ON Direction Change to Source OFF f OSC dc OSC t pd 2.9 40 - - - - - - - - - - 600 100 600 100 600 100 600 100 6.1 60 - - - - - - - - MHz % ns
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Timing Diagram
STROBE
C
D
E
F
G
CLOCK A DATA D19 B D18 D0
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Legend
ID A B C D Description DATA Setup Time DATA Hold Time Setup STROBE-to-CLOCK Rising Edge CLOCK High Pulse Width Value (ns) 15 10 50 50 ID E F G Description CLOCK Low Pulse Width Setup CLOCK Rising Edge-to-STROBE STROBE Pulse Width Value (ns) 50 50 50
Figure 2. Serial Port Write Timing
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 34923 is designed for pulse-width modulated (PWM) current control of DC motors. It is capable of continuous output currents up to 2.0 A and operating voltages of up to 45 V. Internal fixed off-time PWM current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed current decay modes. DIR and PWM/ENABLE input pins are provided for use in controlling the speed and direction of a DC motor with externally applied PWM-control signals. The PWM/ENABLE input can be programmed via the serial port to PWM the bridge in fast or slow current decay. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis and crossover-current protection. Special power-up sequencing is not required.
FUNCTIONAL PIN DESCRIPTION
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VB
This pin provides a node for charge storage at the boost voltage. Internal circuitry will draw VB current from this node, and the charge pump will deliver charge to this node.
DATA
This logic input is the serial data used by the serial interface.
CLOCK
This logic input is the clock for the serial interface. Data is shifted in synchronously with this clock.
CP1 and CP2
These pins are the connections to the switching capacitor in the charge pump. These pins swing between ground and VB, drawing charge from VBB and delivering it to the VB node.
STROBE
This logic input is used to latch data from the serial interface into the internal logic.
DIR
This is the direction input for the H-bridge driver.
VREF
This input provides a reference voltage for the current limit comparator threshold.
PWM/ENABLE
This pin is the enable input for the H-bridge driver. When asserted this will bring the H-bridge out of tri-state mode so that it can drive a load.
DCMA and DCMB
These are the high-current, high-voltage drive signals for the motor.
PWMMODE
This logic input controls the H-bridge output mode when the PWM is deasserted. The H-bridge can have an active or passive output state when the PWM input is deasserted.
VBB
This is the motor drive voltage input. The H-bridge will deliver this voltage to the motor.
OSC
This logic input is the clock for the on-board decay time generator used only when in internal PWM mode. The decay time can be slow or mixed fast and slow.
SPAN
This logic-level input controls the current limit comparator threshold that is generated from VREF.
VDD
This is the power supply input for the internal logic and several other functions.
VREG
This output is a decoupling node for the internal bandgap reference voltage generator.
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FUNCTIONAL DESCRIPTION Serial Interface
The 34923 is controlled via a 3-wire (clock, data, strobe) serial port. The programmable functions allow maximum flexibility in configuring the PWM to the motor drive requirements. The serial data is clocked in starting with bit D19. Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 Function Blank Time LSB Blank Time MSB Fixed Off-Time LSB Fixed Off-Time Bit 1 Fixed Off-Time Bit 2 Fixed Off-Time Bit 3 Fixed Off-Time MSB Fast Decay Time LSB Fast Decay Time Bit 1 Fast Decay Time Bit 2 Fast Decay Time MSB Synchronous Rectification Mode Synchronous Rectification Enable External PWM Decay Mode Enable Logic Direction Logic Divisor SPAN Select Internal PWM Mode Test Mode Sleep Mode
D2-D6, Fixed Off-Time
A five-bit word sets the fixed off-time for internal PWM current control. The off time is defined as follows: t off = (8[1 + N] /fosc) - 1/f osc where N = 0 to 31. For example, with an oscillator frequency of 4.0 MHz, the offtime is adjusted from 1.75 s to 63.75 s in increments of 2.0 s.
D7-D10, Fast Decay Time
A four-bit word sets the fast decay portion of the fixed off-time for the internal PWM control circuitry. This will only have impact if the mixed current decay mode is selected (via bit D17 and the PWMMODE input pin). For t fd > t off, the device will effectively operate in the fast decay mode. The fast decay portion is defined as follows: t fd = (8[1 + N]/f osc) - 1/fosc where N = 0 to 15. For example, with an oscillator frequency of 4.0 MHz, the fast decay time is adjusted from 1.75 s to 31.75 s in increments of 2.0 s.
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D11-D12, Synchronous Rectification Control
The active mode prevents reversal of load current by turning off synchronous rectification when a zero current level is detected. The passive mode will allow reversal of current but will turn off the synchronous rectifier circuit if the load current inversion ramps up to the current limit set by VREF /RS. D11 0 0 1 1 D12 0 1 0 1 Synchronous Rect. Control Disabled Active Disabled Passive
D0-D1, Blank Time
The current-sense comparator is blanked when any output driver is switched on in accordance with the table below. fosc is the oscillator input frequency. D0 0 1 0 1 D1 0 0 1 1 Blank Time 4/f osc 6/f osc 12/f osc 24/f osc
D13, External PWM Decay Mode
Bit D13 determines the current decay mode when using PWM/ENABLE chopping for external PWM current control. D13 0 1 Current Decay Mode Fast Slow
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D14, Enable Logic
Bit D14, in conjunction with the PWM/ENABLE pin, determines if the output drivers are in the chopped (OFF) or ON state. PWM/ ENABLE 0 1 1 0 D14 0 1 0 1 Operating Mode Chopped ON
D19, Sleep Mode
Bit D19 selects a Sleep mode to minimize power consumption when not in use. This disables much of the internal circuitry, including the regulator and charge pump. On power-up the serial port is initialized to all zeros. Bit D19 should be programmed high for 1.0 ms before attempting to enable any output driver. D19 0 1 Sleep Mode Sleep Normal
Serial Port Write Timing Operations
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D15, Direction Logic
Bit D15, in conjunction with the DIR pin, determines if the device is operating in the forward or reverse state. State Reverse Forward DIR 0 1 1 0 D15 0 1 0 1 DCMA Low High DCMB High Low
Data is clocked into the shift register on the rising edge of the CLOCK signal. Normally STROBE will be held high, only brought low to initiate a write cycle. Refer to Figure 2, Serial Port Write Timing, page 8, for the minimum timing requirements.
VREG
This internally generated voltage is used to operate the sinkside outputs. The VREG pin should be decoupled with a 0.22 F capacitor to ground. VREG is internally monitored and, in the case of a fault condition, the outputs of the device are disabled.
D16, Divisor SPAN Select
Bit D16, in conjunction with the SPAN pin, determines if VREF is divided by 5 or 10. Divisor /5 /10 SPAN 1 0 0 1 D16 0 1 0 1
Charge Pump
The charge pump is used to generate a gate supply voltage greater than VBB to drive the source-side gates. A 0.22 F ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 F ceramic capacitor should be connected between VB and VBB to act as a reservoir to operate the high-side devices. The VB voltage is internally monitored and, in the case of a fault condition, the source outputs of the device are disabled.
Shutdown
In the event of a fault (excessive junction temperature or low voltage on VB or VREG), the outputs of the device are disabled until the fault condition is removed. At power-up, and in the event of low VDD, the Undervoltage Lockout circuit disables the drivers and resets the data in the serial port to all zeros.
D17, Internal PWM Mode
Bit D17, in conjunction with the PWMMODE pin, selects mixed or slow current decay. PWMMODE 0 1 1 0 D17 0 1 0 1 Current Decay Mode Mixed Slow
PWM Timer Function
The PWM timer is programmable via the serial port (bits D2- D10) to provide off-time PWM signals to the control circuitry. In the mixed current-decay mode, the first portion of the off time operates in fast decay, until the fast decay time count (serial bits D7-D10) is reached, followed by slow decay for the rest of the off-time period (bits D2-D6). If the fast decay time is set longer than the off time, the device effectively operates in fast decay mode. Bit D17, in conjunction with PWMMODE, selects mixed or slow decay.
D18, Test Mode
Bit D18 low (default) operates the device in normal mode. D18 is only used for testing purposes. The user should never change this bit.
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PWM Blank Timer
When a source driver turns on, a current spike occurs owing to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source-enable latch, the sense comparator is blanked. The blank timer runs after the off-time counter (see bits D2-D6) to provide the programmable blanking function. The blank timer is reset when PWM/ENABLE is chopped or DIR is changed. For external PWM control, a DIR change or PWM/ENABLE on will trigger the blanking function.
Current Regulation
Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of the H-bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (RS), the applied analog reference voltage (VREF), the SPAN logic level, and serial data bit D16: When SPAN = D16, ITRIP = VREF /10RS When SPAN D16, ITRIP = VREF /5RS At the trip point, the sense comparator resets the sourceenable latch, turning off the source driver. The load inductance then causes the current to recirculate for the serial-portprogrammed fixed off-time period. The current path during recirculation is determined by the configuration of slow/mixed current-decay mode (D17) and the synchronous rectification control bits (D11 and D12).
Synchronous Rectification
When a PWM off cycle is triggered, either by an PWM/ ENABLE chop command or internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The 34923 synchronous rectification feature will turn on the opposite pair of outputs during the current decay and effectively short out the body diodes with the low RDS(ON) driver. This will reduce power dissipation significantly and can eliminate the need for external Schottky diodes. Synchronous rectification can be configured in active mode, passive mode, or disabled via the serial port (bits D11 and D12). The active or passive mode selection has no impact in slowdecay mode. With synchronous rectification enabled, the slowdecay mode serves as an effective brake mode.
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Internal PWM (Current Mode) PWM Frequency
The internal PWM opeating frequency is set by the sum of "Off Time", as determined by bits D2 through D6, "Blank Time", as determined by bits D0 and D1, and the time constant of the motor.
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APPLICATIONS Current Sensing
To minimize inaccuracies in sensing the ITRIP current level, which may be caused by ground trace IR drops, the sense resistor should have an independent ground return to the ground pin of the device. For low-value sense resistors, the IR drops in the PCB sense resistor's traces can be significant and should be taken into account. The use of sockets should be avoided because they can introduce variation in RS owing to their contact resistance. The maximum value of RS is given as RS 0.5/ITRIP.
Layout
The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance (see following Note), the driver should be soldered directly onto the board. The ground side of RS should have an individual path to the ground pins of the device. This path should be as short as is possible physically and should not have any other components connected to it. It is recommended that a 0.1 F capacitor be placed between SENSE and ground as close to the device as possible; the load supply pin, VBB, should be decoupled with an electrolytic capacitor (>47 F is recommended) placed as close to the device as is possible. Note The thermal resistance and absolute maximum allowable package power dissipation specified in the MAXIMUM RATINGS table, page 4, is measured on typical two-sided PCB with minimal copper ground area. For the 34923, RJA can be reduced to 56C/W with 3.57-in2 copper ground area, as shown in Figure 3.
ALLOWABLE PACKAGE POWER DISSIPATION WATTS
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Braking
The braking function is implemented by driving the device in slow-decay mode via serial port bit D13, enabling synchronous rectification via bit D12, and chopping with the combination of D14 and the PWM/ENABLE input pin. Because it is possible to drive current in either direction through the drivers, this configuration effectively shorts out the motor-generated back EMF (BEMF) as long as the PWM/ENABLE chop mode is asserted. It is important to note that the internal PWM currentcontrol circuit will not limit the current when braking, because the current does not flow through the sense resistor. The maximum brake current can be approximated by VBEMF/RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worst-case braking situations of high-speed and high-inertial loads.
5
4
3
Thermal Protection
Circuitry turns off all drivers when the junction temperature reaches 165C typically. It is intended only to protect the device from failures owing to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15C.
2 RJA = 56C/W 1
0 25
50
75
100
125
150
TEMPERATURE (C)
Figure 3. Package Dissipation Temperature Derating
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PACKAGE DIMENSIONS
DW SUFFIX 24-LEAD SOIC WIDE BODY PLASTIC PACKAGE CASE 751E-04 ISSUE E -A24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0 8 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0 8 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
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1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -TSEATING PLANE X 45
M
22X
G
K
DIM A B C D F G J K M P R
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NOTES
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2003 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors
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